1. Technical Field
The present invention relates generally to power management. More particularly, this invention relates to controlling power and performance in a hybrid, multitasking microprocessor system.
2. Discussion of Related Art
In a homogeneous chip-multiprocessor such as POWER6, because the processing elements have similar capabilities and power/performance trade-offs, management can be individually performed with the same algorithm for each processing element.
In a hybrid computing where there are different processing elements, each target is a special purpose/function (e.g., XML, Crypto, massively threaded) having different power/performance trade-offs (e.g., in-order vs. out-of-order, single-thread optimized vs. throughput optimized). The processing elements of a hybrid chip-multiprocessor share resources, such as a common power/thermal budget, on-chip caches and bandwidth, and can have multiple applications running concurrently where each application or task may utilize multiple special-purpose processing elements in sequential or concurrent ordering. Since the processing elements (hereinafter abbreviated as PE) of a hybrid chip-multiprocessor share resources, the conventional power managing (e.g., clock frequency/voltage scaling) decisions that optimize independently for individual PE, or decisions that optimize for all PEs on the chip without considering inter-dependent relationships, result in processing capabilities unique to each PE that are not optimal for the entire hybrid chip-multiprocessor.
In the context of a hybrid, multitasking microprocessor system, a task spans multiple accelerators, which can be compress, xml, crypto, packet processing, etc. in a specific ordering. Unlike a pipeline for micro- or graphics processor, the ordering may be different for each task.
In view of the foregoing, a need exists for a system and method of power management in a hybrid, multitasking microprocessor system.